1. Field of the Invention
The present invention relates to a signal transmitting/receiving apparatus and method in a Single Carrier-Frequency Division Multiplexing Access (SC-FDMA) communication system. More particularly, the present invention relates to a signal transmitting/receiving apparatus and method for reducing power consumption in an SC-FDMA communication system.
2. Description of the Related Art
A Single Carrier-Frequency Division Multiplexing Access (SC-FDMA) scheme is similar to an Orthogonal Frequency Division Multiplexing Access (OFDMA) scheme. However, the SC-FDMA scheme maintains single-carrier properties while using a multi-carrier, thereby lowering a Peak-to-Average Power Ratio (PAPR) which is a problem in the OFDMA scheme.
Unlike a data modulation method of the OFDMA scheme, the SC-FDMA scheme allocates data to a time domain, converts a signal allocated to the time domain into a signal in a frequency domain through the use of a Discrete Fourier Transform (DFT) module, and then performs signal processing with respect to the signal in the frequency domain, thereby generating one SC-FDMA symbol in a time domain. Therefore, a transceiver using the SC-FDMA scheme needs a DFT module, differently from a transceiver using the OFDMA scheme.
FIG. 1 is a block diagram illustrating a configuration of a signal transmission/reception apparatus used in an SC-FDMA communication system according to the related art.
Referring to FIG. 1, a signal transmission apparatus 100 includes an M-point DFT module 101, a subcarrier allocator (or subcarrier mapper) 103, an N-point Inverse Fast Fourier Transform (IFFT) module 105, a Cyclic Prefix (CP) inserter 107, a Parallel-to-Serial (PS) converter 109, a Digital-to-Analog (DA) converter 111, and a Radio Frequency (RF) processor 113. A signal reception apparatus 150 includes an RF processor 151, an Analog-to-Digital (AD) converter 153, a CP remover 155, a Serial-to-Parallel (SP) converter 157, an N-point Fast Fourier Transform (FFT) module 159, a subcarrier de-allocator (or subcarrier de-mapper) 161, an equalizer 163, an M-point Inverse Discrete Fourier Transform (IDFT) module 165, and a detector 167.
First, a signal to be transmitted is generated in the signal transmission apparatus 100, the signal is input to the M-point DFT module 101. The M-point DFT module 101 converts the input signal in a time domain into a signal in a frequency domain, and outputs the signal in the frequency domain to the subcarrier allocator 103. The subcarrier allocator 103 receives the signal output from the M-point DFT module 101, maps the received signal to a frequency band to be transmitted, and outputs the mapped signal to the N-point IFFT module 105. The N-point IFFT module 105 receives the signal output from the subcarrier allocator 103, performs IFFT processing on the signal received from the subcarrier allocator 103, and outputs the IFFT-processed signal to the CP inserter 107. The CP inserter 107 inserts a CP into the signal output from the N-point IFFT module 105, and outputs the CP-inserted signal to the PS converter 109. The PS converter 109 receives a parallel signal output from the CP inserter 107, converts the parallel signal into a serial signal, and outputs the serial signal to the DA converter 111. The DA converter 111 receives a digital signal output from the PS converter 109, converts the digital signal into an analog signal, and outputs the analog signal to the RF processor 113. The RF processor 113 receives the signal output from the DA converter 111, performs an RF processing on the received signal, and outputs the RF-processed signal to the signal reception apparatus 150 through a channel 130.
The operation of the signal reception apparatus 150 for receiving a signal through the channel 130 will now be described. The RF processor 151 receives an RF signal through the channel 130, restores an original signal before the RF processing from the received RF signal, and outputs the restored signal to the AD converter 153. The AD converter 153 receives an analog signal output from the RF processor 151, converts the analog signal into a digital signal, and outputs the digital signal to the CP remover 155. The CP remover 155 removes the CP from the signal output from the AD converter 153, and outputs the CP-removed signal to the SP converter 157. The SP converter 157 receives a serial signal output from the CP remover 155, converts the serial signal into a parallel signal, and outputs the parallel signal to the N-point FFT module 159. The N-point FFT module 159 receives the signal output from the SP converter 157, performs FFT processing on the received signal, and outputs the FFT-processed signal to the subcarrier de-allocator 161. The subcarrier de-allocator 161 receives the signal output from the N-point FFT module 159, demaps the received signal to a signal in the frequency domain, and outputs the demapped signal to the equalizer 163. The equalizer 163 receives the signal output from the subcarrier de-allocator 161, compensates for signal distortion, and outputs the compensated signal to the M-point IDFT module 165. The M-point IDFT module 165 receives the signal in the frequency domain, which has been output from the equalizer 163, converts the signal in the frequency domain into a signal in the time domain, and outputs the signal in the time domain to the detector 167. The detector 167 receives the signal output from the M-point IDFT module 165, and detects a reception signal.
The DFT of the M-point DFT module 101 in the signal transmission apparatus 100 is defined by Equation 1 below:
                              X          ⁡                      [            k            ]                          =                              ∑                          n              =              0                                      M              -              1                                ⁢                                    x              ⁡                              [                n                ]                                      ⁢                          W              M              nk                                                          (        1        )            
The IDFT of the M-point IDFT module 165 in the signal reception apparatus 150 is defined by Equation 2 below:
                              X          ⁡                      [            n            ]                          =                              1            M                    ⁢                                    ∑                              n                =                0                                            M                -                1                                      ⁢                                          X                ⁡                                  [                  k                  ]                                            ⁢                              W                M                                  -                  nk                                                                                        (        2        )            
Respective exponential values, which are multipliers in Equations 1 and 2, are referred to as twiddle factors. For example, the twiddle factor may be defined by Equation 3 below:WM=exp(−j2π/M)  (3)
In Equation 3, “M” denotes the number of points in DFT or IDFT, and may be referred to as the size of DFT or IDFT.
Using a more efficient algorithm for the DFT calculation, the original DFT calculation may be implemented with a combination of smaller DFTs. Such algorithms are collectively designated as FFT. When the number of points in DFT is a power of 2 (i.e., 2n), the DFT and IDFT are implemented through the use of radix-2, radix-4, and split-radix algorithms in order to reduce the number of operations of actual hardware and to achieve a fast operation. In a case where DFT is performed on information with N number of input samples, when FFT with a pipeline structure is used, N*N number of complex multiplications is required. However, in this case, FFT in a butterfly structure is used, N/2*log N number of complex multiplications is required, so that it is possible to reduce the amount of calculation.
Meanwhile, in a Long Term Evolution (LTE) system, which represents the latest version of communication networks of the 3rd Generation Partnership Project (3GPP) series, voice communication together with other data and multimedia communication is an important application due to characteristics of the 3GPP series. The LTE system is an Internet Protocol (IP)-based network, and provides voice communication service through a voice packet network using Voice-over-IP (VoIP).
In terms of an entire network, in order to efficiently configure VoIP, one cell must support a plurality of users. In this case, in order to maximize the system throughput, it is necessary to reduce overheads of control signals. To this end, a Semi-Persistent Scheduling (SPS) scheme which allows a resource allocated to one user to be continuously used is widely employed. The SPS scheme may reduce the overhead which is a problem in a dynamic scheduling scheme. In the case of the LTE system, since the amount of information of data of voice signals is not large, a base station allocates one Resource Block (RB) with a specific period to a mobile terminal through the use of the SPS scheme, and the mobile terminal transmits/receives signals through the use of the allocated resource block.
Also, the mobile terminal may be allocated RBs with different sizes depending on time or depending on Hybrid Automatic Repeat Request (HARQ) process IDentifications (IDs). In this case, the DFT of which the size, i.e., the number of points, changes depending on the size of an RB allocated to the mobile terminal, and the IFFT with a fixed size, because the IFFT is performed according to a system bandwidth, are continuously performed while the mobile terminal is transmitting high-speed data. However, when voice communication is continued during several minutes, it is unnecessary to continuously perform data modulation in a scheme for high-speed data communication, and such an unnecessary operation results in a waste of power.
The following description will be given on power consumed by each block with reference to the aforementioned signal transmission apparatus 100 of FIG. 1 as an example.
In an encoder (not illustrated), which may be positioned at an input end of the M-point DFT module 101, power consumption increases in proportion to the amount of data to be transmitted.
When the M-point DFT module 101 has a single butterfly structure, the M-point DFT module 101 must use faster clocks that are two times the number of stages than clocks used in a pipeline structure in order to output the same throughput as that output in the pipeline structure, thereby consuming relatively more time and power. In order to implement a scalable DFT, which the size is not fixed and the size changes to various scales, a hardware implementation scheme of arranging a plurality of 2-radix, 3-radix, and 5-radix butterfly structures in series according to a pipeline scheme is widely employed. In this case, depending on Transmission Time Intervals (TTIs) or depending on HARQ process IDs, DFTs having different sizes must be used for Adaptive Modulation and Coding (AMC). Accordingly, it is impossible to cut off power of a non-used butterfly structure for a long time, so that almost the same amount of power is consumed regardless of a bandwidth allocated to a mobile terminal or a system bandwidth.
The subcarrier allocator 103 may be implemented simply through address control upon hardware implementation, so that the subcarrier allocator 103 consumes little power.
In the N-point IFFT module 105, since the IFFT size, i.e., the number of points, of the N-point IFFT module 105 is determined according to a determined system bandwidth (e.g., the system bandwidth of 20 MHz results in 2048-point IFFT), power consumption is always constant in accordance with the maximum amount of data to be transmitted.
In the transmission filter, which includes the PS converter 109, the DA converter 111, and the RF processor 113, since power consumption results in proportion to a sampling rate which is determined based on a system bandwidth, additional optimization is impossible. However, since the number of clocks used for the operation of the transmission filter is less than the number of clocks used in the M-point DFT module 101 or N-point IFFT module 105, power consumption is less than the power consumption of the M-point DFT module 101 or N-point IFFT module 105.
That is, regardless of whether the amount of data to be transmitted is large or small, the M-point DFT module 101 and the N-point IFFT module 105 consume almost the same amount of power as the power consumed when the maximum amount of data is transmitted. When data to be transmitted is large, the power efficiency is hardly deteriorated. However, when data to be transmitted is small, the power efficiency is deteriorated, thereby significantly increasing a ratio of the power consumption of the M-point DFT module 101 and N-point IFFT module 105 to the power consumption of the entire system bandwidth.
Therefore, a need exists for an apparatus and method for reducing power consumption in a SC-FDMA communication system.